With demand rising for a TV image of higher and higher quality, an IDTV has recently been developed as a part of the conventional NTSC system intended to remove cross colors, dot interference, line flicker and the like by digital signal processing using a memory on the one hand, while a high-definition TV system having twice as many scanning lines as the NTSC system has been conceived on the other hand. These two systems, however, have different methods of display in terms of aspect ratio, that is, 4:3 for the NTSC and 5:3 for the high-definition system. It is, therefore, necessary to convert the aspect ratio if a TV receiver is to receive television signals of different systems mentioned above.
A conventional TV receiver is disclosed, for example, in JP-A-61-55386 (published application number 62-213389(A)). FIG. 2 shows a configuration of this conventional TV receiver, in which a TV signal of NTSC system (aspect ratio of 4:3) is subjected to an image quality improving process (conversion into non-interlace scanning, i.e., into progressive scanning) and an image is displayed on a high-definition TV receiver (aspect ratio of 5:3). In FIG. 2, reference numeral 11 designates an NTSC signal input terminal of aspect ratio of 4:3, numerals 12, 13 high-definition TV signal input terminals of an aspect ratio of 5:3, numeral 14 an NTSC decoder for demodulating the NTSC signal and producing R, G and B signals together with a sync signal, numeral 15 a non-interlace processing circuit for converting the demodulated R, G, B signals for non-interlace scanning, numeral 16 an RGB switching circuit for switching the signal converted for non-interlace scanning to a high definition TV signal and supplying it to the CRT, numeral 17 a definition switching circuit for switching the sync signal and supplying the same to the CRT, and numeral 18 the CRT having an aspect ratio of 5:3 adapted for displaying both the NTSC signal of aspect ratio of 4:3 and the high-definition TV signal of aspect ratio of 5:3.
The operation of a TV receiver configured as described above will be explained with reference to a display screen having an aspect ratio of 5:3 shown in FIG. 4. In FIG. 2, when an NTSC signal is supplied to the input terminal 11, the NTSC decoder 14 demodulates R, G, B signals and a sync signal and supplies the same signals to the non-interlace processing circuit 15.
The non-interlace processing circuit 15 includes a plurality of line memories for time-base conversion along the horizontal direction and sync signal processing for conversion into non-interlace scanning. The time-base conversion is for compressing the time-base by one half along the horizontal direction in order display on a CRT having an aspect ratio of 4:3 in such a manner that if the signal processing clock of the NTSC decoder is 4 fsc (four times the subcarrier frequency), for instance, the data is written in a line memory with a clock signal of 4 fsc and read out with a clock signal of 8 fsc.
In the case of displaying on a CRT having an aspect ratio of 5:3, on the other hand, the horizontal signal time-base is required to be compressed taking into consideration the time-base compression by one half for non-interface scanning and the difference in aspect ratio. This operation will be explained with reference to the non-interlace processing circuit 15 shown in FIG. 3.
In FIG. 3, numerals 150, 151 designate line memories for the time-base conversion, numeral 152 a write clock signal generator for the line memories 150, 151, numeral 153 a read clock signal generator, and numerals 154, 155 read and write switches respectively switchable in state every horizontal period in such a way that when the write switch is switched to one of the line memories 150 and 151, the read switch 155 is switched to the other thereof.
In the above-mentioned configuration, an R signal, for example, supplied from the NTSC decoder 4 is supplied to the line memory 151 through the write switch 154 of the non-interlace processing circuit 15. The R signal for a given horizontal period, for example, is written in a line memory in response to a write clock signal (a clock signal of 4 fsc, if the clock frequency for signal processing of the NTSC decoder is 4 fsc) produced from the write clock signal generator 152. In the case of writing in the line memory 151, the R signal for one horizontal period written in the preceding horizontal period is read from the line memory 152 twice in succession in response to a read clock signal (a clock signal of a clock frequency of 10 fsc (=8 fsc.times.5/4 in order for the conversion into non-interlace scanning and the different aspect ratio) generated from the read clock signal generator 152, and the signal thus read is applied to the RGB switching circuit 16 as a non-interlace signal through the read switch 15. The write and read clock signal generators 152, 153 are configured as a PLL circuit or the like and are controlled by a sync signal for the NTSC signal. The output signal which was converted for the non-interlace scanning and for the different aspect ratio by the non-interlace processing circuit 17 is displayed on the CRT 18 through the RGB switching circuit 16. The sync signal is compressed to be doubled regardless of the aspect ratio and is supplied through the deflection switching circuit 17 to the CRT 18.
In contrast, in the case of inputting a high-definition signal to the input terminal 12, high-definition R, G, B signals together with horizontal and vertical deflection signals are supplied through the RGB switching circuit 16 and the deflection switching circuit 17 to the CRT 18 for display thereon. FIG. 4 shows the display state, in which a video signal (signal obtained by subjecting an NTSC signal to the non-interlace conversion processing and the aspect-ratio conversion processing) having an aspect ratio of 4:3 is displayed on the CRT 18 having an aspect ratio of 5:3. Character A designates a residual non-display portion.
In the aforementioned configuration, however, the clock signal for processing of non-interlace scanning and aspect ratio conversion is 18 fsc, that is, the number of clocks per one horizontal period is an odd number (227.5.times.10=2275). As a result, the number of clocks for the time-base compressed horizontal period is 2275/2, so that the processing circuit for non-interlace scanning conversion requires a delay of 1/2 clocks for each line, and is thus complicated.